68a2250886
We started actually running up against the page boundary for kernel stacks and thus double-faulting on page faults from kernel space. So I finally added IST stacks. Note that we currently just increment/decrement the IST entry by a page when we enter the handler to avoid clobbering on re-entry, but this means: * these handlers need to be able to operate with only a page of stack * kernel stacks always have to be >1 pages * the amount of nesting possible is tied to the kernel stack size. These seem fine for now, but we should maybe find a way to use something besides g_kernel_stacks to set up the IST stacks if/when this becomes an issue.
62 lines
960 B
ArmAsm
62 lines
960 B
ArmAsm
%include "push_all.inc"
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extern isr_handler
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global isr_handler_prelude
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isr_handler_prelude:
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push_all
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check_swap_gs
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mov rdi, rsp
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mov rsi, rsp
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call isr_handler
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jmp isr_handler_return
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extern irq_handler
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global irq_handler_prelude
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irq_handler_prelude:
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push_all
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check_swap_gs
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mov rdi, rsp
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mov rsi, rsp
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call irq_handler
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; fall through to isr_handler_return
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global isr_handler_return
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isr_handler_return:
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check_swap_gs
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pop_all
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add rsp, 16 ; because the ISRs added err/num
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iretq
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%macro EMIT_ISR 2
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global %1
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%1:
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push 0
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push %2
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jmp isr_handler_prelude
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%endmacro
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%macro EMIT_EISR 2
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global %1
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%1:
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push %2
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jmp isr_handler_prelude
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%endmacro
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%macro EMIT_IRQ 2
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global %1
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%1:
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push 0
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push %2
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jmp irq_handler_prelude
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%endmacro
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%define EISR(i, s, name) EMIT_EISR name, i ; ISR with error code
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%define ISR(i, s, name) EMIT_ISR name, i
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%define IRQ(i, q, name) EMIT_IRQ name, i
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section .isrs
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%include "interrupt_isrs.inc"
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