f0025dbc47
Now that the other CPUs have been brought up, add support for scheduling tasks on them. The scheduler now maintains separate ready/blocked lists per CPU, and CPUs will attempt to balance load via periodic work stealing. Other changes as a result of this: - The device manager no longer creates a local APIC object, but instead just gathers relevant info from the APCI tables. Each CPU creates its own local APIC object. This also spurred the APIC timer calibration to become a static value, as all APICs are assumed to be symmetrical. - Fixed a bug where the scheduler was popping the current task off of its ready list, however the current task is never on the ready list (except the idle task was first set up as both current and ready). This was causing the lists to get into bad states. Now a task can only ever be current or in a ready or blocked list. - Got rid of the unused static process::s_processes list of all processes, instead of trying to synchronize it via locks. - Added spinlocks for synchronization to the scheduler and logger objects.
147 lines
4.2 KiB
C++
147 lines
4.2 KiB
C++
#pragma once
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/// \file apic.h
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/// Classes to control both local and I/O APICs.
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#include <stdint.h>
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#include "kutil/enum_bitfields.h"
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enum class isr : uint8_t;
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/// Base class for other APIC types
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class apic
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{
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public:
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/// Constructor
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/// \arg base Physical base address of the APIC's MMIO registers
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apic(uintptr_t base);
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protected:
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uint32_t *m_base;
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};
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enum class ipi : uint32_t
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{
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// Delivery modes
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fixed = 0x0000,
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smi = 0x0200,
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nmi = 0x0400,
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init = 0x0500,
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startup = 0x0600,
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// Flags
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deassert = 0x0000,
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assert = 0x4000,
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edge = 0x0000, ///< edge-triggered
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level = 0x8000, ///< level-triggered
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};
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IS_BITFIELD(ipi);
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/// Controller for processor-local APICs
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class lapic :
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public apic
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{
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public:
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/// Constructor
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/// \arg base Physicl base address of the APIC's MMIO registers
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lapic(uintptr_t base);
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/// Get the local APIC's ID
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uint8_t get_id();
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/// Send an inter-processor interrupt.
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/// \arg mode The sending mode
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/// \arg vector The interrupt vector
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/// \arg dest The APIC ID of the destination
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void send_ipi(ipi mode, uint8_t vector, uint8_t dest);
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/// Send an inter-processor broadcast interrupt to all other CPUs
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/// \arg mode The sending mode
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/// \arg self If true, include this CPU in the broadcast
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/// \arg vector The interrupt vector
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void send_ipi_broadcast(ipi mode, bool self, uint8_t vector);
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/// Wait for an IPI to finish sending. This is done automatically
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/// before sending another IPI with send_ipi().
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void ipi_wait();
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/// Enable interrupts for the LAPIC timer.
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/// \arg vector Interrupt vector the timer should use
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/// \arg repeat If false, this timer is one-off, otherwise repeating
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void enable_timer(isr vector, bool repeat = true);
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/// Reset the timer countdown.
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/// \arg interval The interval in us before an interrupt, or 0 to stop the timer
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/// \returns The interval in us that was remaining before reset
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uint32_t reset_timer(uint64_t interval);
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/// Stop the timer.
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/// \returns The interval in us remaining before an interrupt was to happen
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inline uint32_t stop_timer() { return reset_timer(0); }
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/// Enable interrupts for the LAPIC LINT0 pin.
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/// \arg num Local interrupt number (0 or 1)
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/// \arg vector Interrupt vector LINT0 should use
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/// \arg nmi Whether this interrupt is NMI delivery mode
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/// \arg flags Flags for mode/polarity (ACPI MPS INTI flags)
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void enable_lint(uint8_t num, isr vector, bool nmi, uint16_t flags);
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void enable(); ///< Enable servicing of interrupts
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void disable(); ///< Disable (temporarily) servicing of interrupts
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/// Calibrate the timer speed against the clock
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void calibrate_timer();
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private:
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inline static uint64_t ticks_to_us(uint64_t ticks) { return ticks / s_ticks_per_us; }
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inline static uint64_t us_to_ticks(uint64_t interval) { return interval * s_ticks_per_us; }
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void set_divisor(uint8_t divisor);
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void set_repeat(bool repeat);
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uint32_t m_divisor;
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static uint64_t s_ticks_per_us;
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};
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/// Controller for I/O APICs
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class ioapic :
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public apic
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{
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public:
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/// Constructor
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/// \arg base Physical base address of the APIC's MMIO registers
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/// \arg base_gsi Starting global system interrupt number of this IOAPIC
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ioapic(uintptr_t base, uint32_t base_gsi);
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uint32_t get_base_gsi() const { return m_base_gsi; }
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uint32_t get_num_gsi() const { return m_num_gsi; }
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/// Set a redirection entry.
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/// TODO: pick CPU
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/// \arg source Source interrupt number
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/// \arg vector Interrupt vector that should be used
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/// \arg flags Flags for mode/polarity (ACPI MPS INTI flags)
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/// \arg masked Whether the iterrupt should be suppressed
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void redirect(uint8_t irq, isr vector, uint16_t flags, bool masked);
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/// Mask or unmask an interrupt to stop/start having it sent to the CPU
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/// \arg irq The IOAPIC-local irq number
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/// \arg masked Whether to suppress this interrupt
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void mask(uint8_t irq, bool masked);
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/// Mask all interrupts on this IOAPIC.
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void mask_all() { for(int i=0; i<m_num_gsi; ++i) mask(i, true); }
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/// Unmask all interrupts on this IOAPIC.
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void unmask_all() { for(int i=0; i<m_num_gsi; ++i) mask(i, false); }
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void dump_redirs() const;
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private:
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uint32_t m_base_gsi;
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uint32_t m_num_gsi;
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uint8_t m_id;
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uint8_t m_version;
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};
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