f0025dbc47
Now that the other CPUs have been brought up, add support for scheduling tasks on them. The scheduler now maintains separate ready/blocked lists per CPU, and CPUs will attempt to balance load via periodic work stealing. Other changes as a result of this: - The device manager no longer creates a local APIC object, but instead just gathers relevant info from the APCI tables. Each CPU creates its own local APIC object. This also spurred the APIC timer calibration to become a static value, as all APICs are assumed to be symmetrical. - Fixed a bug where the scheduler was popping the current task off of its ready list, however the current task is never on the ready list (except the idle task was first set up as both current and ready). This was causing the lists to get into bad states. Now a task can only ever be current or in a ready or blocked list. - Got rid of the unused static process::s_processes list of all processes, instead of trying to synchronize it via locks. - Added spinlocks for synchronization to the scheduler and logger objects.
150 lines
2.4 KiB
ArmAsm
150 lines
2.4 KiB
ArmAsm
%include "tasking.inc"
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section .ap_startup
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BASE equ 0x8000 ; Where the kernel will map this at runtime
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CR0_PE equ (1 << 0)
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CR0_MP equ (1 << 1)
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CR0_ET equ (1 << 4)
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CR0_NE equ (1 << 5)
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CR0_WP equ (1 << 16)
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CR0_PG equ (1 << 31)
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CR0_VAL equ CR0_PE|CR0_MP|CR0_ET|CR0_NE|CR0_WP|CR0_PG
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CR4_DE equ (1 << 3)
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CR4_PAE equ (1 << 5)
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CR4_MCE equ (1 << 6)
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CR4_PGE equ (1 << 7)
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CR4_OSFXSR equ (1 << 9)
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CR4_OSCMMEXCPT equ (1 << 10)
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CR4_FSGSBASE equ (1 << 16)
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CR4_PCIDE equ (1 << 17)
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CR4_INIT equ CR4_PAE|CR4_PGE
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CR4_VAL equ CR4_DE|CR4_PAE|CR4_MCE|CR4_PGE|CR4_OSFXSR|CR4_OSCMMEXCPT|CR4_FSGSBASE|CR4_PCIDE
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EFER_MSR equ 0xC0000080
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EFER_SCE equ (1 << 0)
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EFER_LME equ (1 << 8)
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EFER_NXE equ (1 << 11)
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EFER_VAL equ EFER_SCE|EFER_LME|EFER_NXE
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bits 16
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default rel
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align 8
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global ap_startup
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ap_startup:
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jmp .start_real
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align 8
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.pml4: dq 0
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.cpu: dq 0
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.ret: dq 0
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align 16
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.gdt:
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dq 0x0 ; Null GDT entry
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dq 0x00209A0000000000 ; Code
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dq 0x0000920000000000 ; Data
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align 4
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.gdtd:
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dw ($ - .gdt)
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dd BASE + (.gdt - ap_startup)
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align 4
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.idtd:
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dw 0 ; zero-length IDT descriptor
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dd 0
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.start_real:
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cli
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cld
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xor ax, ax
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mov ds, ax
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; set the temporary null IDT
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lidt [BASE + (.idtd - ap_startup)]
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; Enter long mode
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mov eax, cr4
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or eax, CR4_INIT
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mov cr4, eax
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mov eax, [BASE + (.pml4 - ap_startup)]
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mov cr3, eax
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mov ecx, EFER_MSR
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rdmsr
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or eax, EFER_VAL
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wrmsr
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mov eax, CR0_VAL
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mov cr0, eax
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; Set the temporary minimal GDT
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lgdt [BASE + (.gdtd - ap_startup)]
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jmp (1 << 3):(BASE + (.start_long - ap_startup))
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bits 64
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default abs
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align 8
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.start_long:
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; set data segments
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mov ax, (2 << 3)
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mov ds, ax
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mov es, ax
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mov fs, ax
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mov gs, ax
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mov ss, ax
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mov eax, CR4_VAL
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mov rdi, [BASE + (.cpu - ap_startup)]
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mov rax, [rdi + CPU_DATA.rsp0]
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mov rsp, rax
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mov rax, [BASE + (.ret - ap_startup)]
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jmp rax
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global ap_startup_code_size
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ap_startup_code_size:
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dq ($ - ap_startup)
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section .text
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global init_ap_trampoline
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init_ap_trampoline:
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push rbp
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mov rbp, rsp
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; rdi is the kernel pml4
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mov [BASE + (ap_startup.pml4 - ap_startup)], rdi
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; rsi is the cpu data for this AP
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mov [BASE + (ap_startup.cpu - ap_startup)], rsi
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; rdx is the address to jump to
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mov [BASE + (ap_startup.ret - ap_startup)], rdx
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; rcx is the processor id
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mov rdi, rdx
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pop rbp
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ret
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extern long_ap_startup
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global ap_idle
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ap_idle:
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call long_ap_startup
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sti
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.hang:
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hlt
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jmp .hang
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