267 lines
6.0 KiB
C++
267 lines
6.0 KiB
C++
#include "kutil/assert.h"
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#include "apic.h"
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#include "interrupts.h"
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#include "io.h"
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#include "log.h"
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#include "page_manager.h"
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static uint32_t
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apic_read(uint32_t volatile *apic, uint16_t offset)
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{
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return *(apic + offset/sizeof(uint32_t));
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}
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static void
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apic_write(uint32_t volatile *apic, uint16_t offset, uint32_t value)
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{
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*(apic + offset/sizeof(uint32_t)) = value;
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}
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static uint32_t
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ioapic_read(uint32_t volatile *base, uint8_t reg)
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{
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*base = reg;
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return *(base + 4);
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}
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static void
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ioapic_write(uint32_t volatile *base, uint8_t reg, uint32_t value)
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{
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*base = reg;
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*(base + 4) = value;
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}
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apic::apic(uint32_t *base) :
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m_base(base)
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{
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// Map 1MiB of space for the APIC registers and
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// MSI area
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page_manager::get()->map_offset_pointer(
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reinterpret_cast<void **>(&m_base),
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0x100000);
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}
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lapic::lapic(uint32_t *base, isr spurious) :
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apic(base)
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{
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// TODO: This causes a "reserved" page fault under KVM
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apic_write(m_base, 0xf0, static_cast<uint32_t>(spurious));
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log::info(logs::apic, "LAPIC created, base %lx", m_base);
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}
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void
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lapic::calibrate_timer()
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{
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interrupts_disable();
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log::info(logs::apic, "Calibrating APIC timer...");
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// Set up PIT sleep
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uint8_t command = 0x30; // channel 0, loybyte/highbyte, mode 0
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outb(0x43, command);
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const uint32_t initial = -1u;
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enable_timer_internal(isr::isrSpurious, 1, initial, false);
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const int iterations = 5;
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for (int i=0; i<iterations; ++i) {
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const uint16_t pit_33ms = 39375;
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uint16_t pit_count = pit_33ms;
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outb(0x40, pit_count & 0xff);
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io_wait();
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outb(0x40, (pit_count >> 8) & 0xff);
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while (pit_count <= pit_33ms) {
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outb(0x43, 0); // latch counter values
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pit_count =
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static_cast<uint16_t>(inb(0x40)) |
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static_cast<uint16_t>(inb(0x40)) << 8;
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}
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}
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uint32_t remain = stop_timer();
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uint32_t ticks_total = initial - remain;
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m_ticks_per_us = ticks_total / (iterations * 33000);
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log::info(logs::apic, "APIC timer ticks %d times per nanosecond.", m_ticks_per_us);
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interrupts_enable();
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}
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uint32_t
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lapic::enable_timer_internal(isr vector, uint8_t divisor, uint32_t count, bool repeat)
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{
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uint32_t divbits = 0;
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switch (divisor) {
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case 1: divbits = 0xb; break;
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case 2: divbits = 0x0; break;
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case 4: divbits = 0x1; break;
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case 8: divbits = 0x2; break;
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case 16: divbits = 0x3; break;
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case 32: divbits = 0x8; break;
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case 64: divbits = 0x9; break;
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case 128: divbits = 0xa; break;
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default:
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kassert(0, "Invalid divisor passed to lapic::enable_timer");
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}
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uint32_t lvte = static_cast<uint8_t>(vector);
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if (repeat)
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lvte |= 0x20000;
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log::debug(logs::apic, "Enabling APIC timer count %ld, divisor %d, isr %02x",
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count, divisor, vector);
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apic_write(m_base, 0x320, lvte);
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apic_write(m_base, 0x3e0, divbits);
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reset_timer(count);
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return count;
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}
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uint32_t
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lapic::enable_timer(isr vector, uint64_t interval, bool repeat)
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{
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uint64_t ticks = interval * m_ticks_per_us;
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int divisor = 1;
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while (ticks > -1u) {
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ticks /= 2;
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divisor *= 2;
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}
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return enable_timer_internal(vector, divisor, static_cast<uint32_t>(ticks), repeat);
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}
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uint32_t
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lapic::reset_timer(uint32_t count)
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{
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uint32_t remaining = apic_read(m_base, 0x390);
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apic_write(m_base, 0x380, count);
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return remaining;
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}
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void
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lapic::enable_lint(uint8_t num, isr vector, bool nmi, uint16_t flags)
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{
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kassert(num == 0 || num == 1, "Invalid LINT passed to lapic::enable_lint.");
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uint16_t off = num ? 0x360 : 0x350;
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uint32_t lvte = static_cast<uint8_t>(vector);
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uint16_t polarity = flags & 0x3;
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if (polarity == 3)
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lvte |= (1 << 13);
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uint16_t trigger = (flags >> 2) & 0x3;
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if (trigger == 3)
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lvte |= (1 << 15);
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apic_write(m_base, off, lvte);
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log::debug(logs::apic, "APIC LINT%d enabled as %s %d %s-triggered, active %s.",
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num, nmi ? "NMI" : "ISR", vector,
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polarity == 3 ? "level" : "edge",
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trigger == 3 ? "low" : "high");
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}
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void
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lapic::enable()
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{
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apic_write(m_base, 0xf0,
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apic_read(m_base, 0xf0) | 0x100);
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log::debug(logs::apic, "LAPIC enabled!");
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}
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void
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lapic::disable()
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{
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apic_write(m_base, 0xf0,
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apic_read(m_base, 0xf0) & ~0x100);
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log::debug(logs::apic, "LAPIC disabled.");
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}
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ioapic::ioapic(uint32_t *base, uint32_t base_gsi) :
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apic(base),
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m_base_gsi(base_gsi)
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{
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uint32_t id = ioapic_read(m_base, 0);
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uint32_t version = ioapic_read(m_base, 1);
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m_id = (id >> 24) & 0xff;
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m_version = version & 0xff;
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m_num_gsi = (version >> 16) & 0xff;
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log::debug(logs::apic, "IOAPIC %d loaded, version %d, GSIs %d-%d",
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m_id, m_version, base_gsi, base_gsi + (m_num_gsi - 1));
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for (uint8_t i = 0; i < m_num_gsi; ++i) {
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uint16_t flags = (i < 0x10) ? 0 : 0xf;
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isr vector = isr::irq00 + i;
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redirect(i, vector, flags, true);
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}
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}
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void
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ioapic::redirect(uint8_t irq, isr vector, uint16_t flags, bool masked)
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{
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uint64_t entry = static_cast<uint64_t>(vector);
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uint16_t polarity = flags & 0x3;
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if (polarity == 3)
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entry |= (1 << 13);
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uint16_t trigger = (flags >> 2) & 0x3;
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if (trigger == 3)
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entry |= (1 << 15);
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if (masked)
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entry |= (1 << 16);
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ioapic_write(m_base, (2 * irq) + 0x10, static_cast<uint32_t>(entry & 0xffffffff));
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ioapic_write(m_base, (2 * irq) + 0x11, static_cast<uint32_t>(entry >> 32));
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}
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void
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ioapic::mask(uint8_t irq, bool masked)
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{
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uint32_t entry = ioapic_read(m_base, (2 * irq) + 0x10);
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if (masked)
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entry |= (1 << 16);
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else
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entry &= ~(1 << 16);
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ioapic_write(m_base, (2 * irq) + 0x10, entry);
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}
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void
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ioapic::dump_redirs() const
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{
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log::debug(logs::apic, "IOAPIC %d redirections:", m_id);
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for (uint8_t i = 0; i < m_num_gsi; ++i) {
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uint64_t low = ioapic_read(m_base, 0x10 + (2 *i));
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uint64_t high = ioapic_read(m_base, 0x10 + (2 *i));
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uint64_t redir = low | (high << 32);
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if (redir == 0) continue;
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uint8_t vector = redir & 0xff;
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uint8_t mode = (redir >> 8) & 0x7;
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uint8_t dest_mode = (redir >> 11) & 0x1;
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uint8_t polarity = (redir >> 13) & 0x1;
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uint8_t trigger = (redir >> 15) & 0x1;
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uint8_t mask = (redir >> 16) & 0x1;
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uint8_t dest = (redir >> 56) & 0xff;
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log::debug(logs::apic, " %2d: vec %3d %s active, %s-triggered %s dest %d: %x",
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m_base_gsi + i, vector,
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polarity ? "low" : "high",
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trigger ? "level" : "edge",
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mask ? "masked" : "",
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dest_mode,
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dest);
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}
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}
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