515 lines
12 KiB
C++
515 lines
12 KiB
C++
#include <stddef.h>
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#include <stdint.h>
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#include "kutil/enum_bitfields.h"
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#include "kutil/memory.h"
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#include "console.h"
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#include "device_manager.h"
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#include "interrupts.h"
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#include "io.h"
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#include "log.h"
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enum class gdt_type : uint8_t
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{
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accessed = 0x01,
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read_write = 0x02,
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conforming = 0x04,
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execute = 0x08,
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system = 0x10,
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ring1 = 0x20,
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ring2 = 0x40,
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ring3 = 0x60,
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present = 0x80
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};
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IS_BITFIELD(gdt_type);
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struct gdt_descriptor
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{
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uint16_t limit_low;
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uint16_t base_low;
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uint8_t base_mid;
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gdt_type type;
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uint8_t size;
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uint8_t base_high;
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} __attribute__ ((packed));
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struct idt_descriptor
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{
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uint16_t base_low;
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uint16_t selector;
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uint8_t ist;
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uint8_t flags;
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uint16_t base_mid;
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uint32_t base_high;
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uint32_t reserved; // must be zero
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} __attribute__ ((packed));
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struct table_ptr
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{
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uint16_t limit;
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uint64_t base;
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} __attribute__ ((packed));
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gdt_descriptor g_gdt_table[10];
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idt_descriptor g_idt_table[256];
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table_ptr g_gdtr;
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table_ptr g_idtr;
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struct registers;
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extern "C" {
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void idt_write();
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void idt_load();
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void gdt_write(uint16_t cs, uint16_t ds);
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void gdt_load();
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void isr_handler(registers);
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void irq_handler(registers);
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#define ISR(i, name) extern void name ();
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#define EISR(i, name) extern void name ();
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#define IRQ(i, q, name) extern void name ();
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#include "interrupt_isrs.inc"
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#undef IRQ
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#undef EISR
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#undef ISR
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}
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void idt_dump(const table_ptr &table);
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void gdt_dump(const table_ptr &table);
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isr
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operator+(const isr &lhs, int rhs)
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{
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using under_t = std::underlying_type<isr>::type;
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return static_cast<isr>(static_cast<under_t>(lhs) + rhs);
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}
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uint8_t
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get_irq(unsigned vector)
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{
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switch (vector) {
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#define ISR(i, name)
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#define EISR(i, name)
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#define IRQ(i, q, name) case i : return q;
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#include "interrupt_isrs.inc"
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#undef IRQ
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#undef EISR
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#undef ISR
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default: return 0xff;
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}
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}
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void
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set_gdt_entry(uint8_t i, uint32_t base, uint64_t limit, bool is64, gdt_type type)
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{
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g_gdt_table[i].limit_low = limit & 0xffff;
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g_gdt_table[i].size = (limit >> 16) & 0xf;
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g_gdt_table[i].size |= (is64 ? 0xa0 : 0xc0);
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g_gdt_table[i].base_low = base & 0xffff;
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g_gdt_table[i].base_mid = (base >> 16) & 0xff;
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g_gdt_table[i].base_high = (base >> 24) & 0xff;
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g_gdt_table[i].type = type | gdt_type::system | gdt_type::present;
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}
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void
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set_idt_entry(uint8_t i, uint64_t addr, uint16_t selector, uint8_t flags)
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{
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g_idt_table[i].base_low = addr & 0xffff;
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g_idt_table[i].base_mid = (addr >> 16) & 0xffff;
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g_idt_table[i].base_high = (addr >> 32) & 0xffffffff;
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g_idt_table[i].selector = selector;
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g_idt_table[i].flags = flags;
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g_idt_table[i].ist = 0;
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g_idt_table[i].reserved = 0;
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}
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static void
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disable_legacy_pic()
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{
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static const uint16_t PIC1 = 0x20;
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static const uint16_t PIC2 = 0xa0;
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// Mask all interrupts
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outb(0xa1, 0xff);
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outb(0x21, 0xff);
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// Start initialization sequence
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outb(PIC1, 0x11); io_wait();
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outb(PIC2, 0x11); io_wait();
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// Remap into ignore ISRs
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outb(PIC1+1, static_cast<uint8_t>(isr::isrIgnore0)); io_wait();
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outb(PIC2+1, static_cast<uint8_t>(isr::isrIgnore0)); io_wait();
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// Tell PICs about each other
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outb(PIC1+1, 0x04); io_wait();
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outb(PIC2+1, 0x02); io_wait();
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}
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static void
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enable_serial_interrupts()
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{
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uint8_t ier = inb(COM1+1);
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outb(COM1+1, ier | 0x1);
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}
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void
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interrupts_init()
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{
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kutil::memset(&g_gdt_table, 0, sizeof(g_gdt_table));
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kutil::memset(&g_idt_table, 0, sizeof(g_idt_table));
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g_gdtr.limit = sizeof(g_gdt_table) - 1;
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g_gdtr.base = reinterpret_cast<uint64_t>(&g_gdt_table);
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set_gdt_entry(1, 0, 0xfffff, true, gdt_type::read_write | gdt_type::execute);
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set_gdt_entry(2, 0, 0xfffff, true, gdt_type::read_write);
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set_gdt_entry(3, 0, 0xfffff, true, gdt_type::ring3 | gdt_type::read_write | gdt_type::execute);
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set_gdt_entry(4, 0, 0xfffff, true, gdt_type::ring3 | gdt_type::read_write);
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gdt_write(1 << 3, 2 << 3);
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g_idtr.limit = sizeof(g_idt_table) - 1;
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g_idtr.base = reinterpret_cast<uint64_t>(&g_idt_table);
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#define ISR(i, name) set_idt_entry(i, reinterpret_cast<uint64_t>(& name), 0x08, 0x8e);
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#define EISR(i, name) set_idt_entry(i, reinterpret_cast<uint64_t>(& name), 0x08, 0x8e);
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#define IRQ(i, q, name) set_idt_entry(i, reinterpret_cast<uint64_t>(& name), 0x08, 0x8e);
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#include "interrupt_isrs.inc"
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#undef IRQ
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#undef EISR
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#undef ISR
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idt_write();
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disable_legacy_pic();
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enable_serial_interrupts();
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log::info(logs::boot, "Interrupts enabled.");
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}
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struct registers
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{
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uint64_t ds;
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uint64_t rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax;
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uint64_t interrupt, errorcode;
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uint64_t rip, cs, eflags, user_esp, ss;
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};
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#define print_reg(name, value) cons->printf(" %s: %016lx\n", name, (value));
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extern "C" uint64_t get_frame(int frame);
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void
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print_stacktrace(int skip = 0)
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{
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console *cons = console::get();
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int frame = 0;
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uint64_t bp = get_frame(skip);
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while (bp) {
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cons->printf(" frame %2d: %lx\n", frame, bp);
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bp = get_frame(++frame + skip);
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}
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}
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void
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isr_handler(registers regs)
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{
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console *cons = console::get();
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switch (static_cast<isr>(regs.interrupt & 0xff)) {
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case isr::isrTimer:
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cons->puts("\nTICK\n");
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break;
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case isr::isrLINT0:
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cons->puts("\nLINT0\n");
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break;
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case isr::isrLINT1:
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cons->puts("\nLINT1\n");
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break;
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case isr::isrIgnore0:
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case isr::isrIgnore1:
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case isr::isrIgnore2:
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case isr::isrIgnore3:
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case isr::isrIgnore4:
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case isr::isrIgnore5:
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case isr::isrIgnore6:
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case isr::isrIgnore7:
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/*
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cons->printf("\nIGNORED PIC INTERRUPT %d\n",
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(regs.interrupt % 0xff) - 0xf0);
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*/
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break;
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case isr::isrGPFault: {
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cons->set_color(9);
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cons->puts("\nGeneral Protection Fault:\n");
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cons->set_color();
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cons->puts(" flags:");
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if (regs.errorcode & 0x01) cons->puts(" external");
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int index = (regs.errorcode & 0xf8) >> 3;
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if (index) {
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switch (regs.errorcode & 0x06) {
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case 0:
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cons->printf(" GDT[%d]\n", index);
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gdt_dump(g_gdtr);
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break;
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case 1:
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case 3:
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cons->printf(" IDT[%d]\n", index);
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idt_dump(g_idtr);
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break;
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default:
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cons->printf(" LDT[%d]??\n", index);
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break;
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}
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} else {
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cons->putc('\n');
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}
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cons->puts("\n");
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print_reg(" ds", regs.ds);
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print_reg(" cs", regs.cs);
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print_reg(" ss", regs.ss);
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cons->puts("\n");
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print_reg("rax", regs.rax);
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print_reg("rbx", regs.rbx);
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print_reg("rcx", regs.rcx);
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print_reg("rdx", regs.rdx);
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print_reg("rdi", regs.rdi);
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print_reg("rsi", regs.rsi);
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cons->puts("\n");
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print_reg("rbp", regs.rbp);
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print_reg("rsp", regs.rsp);
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cons->puts("\n");
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print_reg("rip", regs.rip);
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print_stacktrace(2);
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cons->puts("\nStack:\n");
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uint64_t sp = regs.rsp;
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while (sp <= regs.rbp) {
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cons->printf("%016x: %016x\n", sp, *reinterpret_cast<uint64_t *>(sp));
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sp += sizeof(uint64_t);
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}
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}
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while(1) asm("hlt");
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break;
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case isr::isrPageFault: {
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cons->set_color(11);
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cons->puts("\nPage Fault:\n");
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cons->set_color();
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cons->puts(" flags:");
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if (regs.errorcode & 0x01) cons->puts(" present");
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if (regs.errorcode & 0x02) cons->puts(" write");
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if (regs.errorcode & 0x04) cons->puts(" user");
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if (regs.errorcode & 0x08) cons->puts(" reserved");
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if (regs.errorcode & 0x10) cons->puts(" ip");
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cons->puts("\n");
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uint64_t cr2 = 0;
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__asm__ __volatile__ ("mov %%cr2, %0" : "=r"(cr2));
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print_reg("cr2", cr2);
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print_reg("rip", regs.rip);
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cons->puts("\n");
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print_stacktrace(2);
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}
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while(1) asm("hlt");
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break;
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case isr::isrAssert: {
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cons->set_color();
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cons->puts("\n");
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print_reg("rax", regs.rax);
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print_reg("rbx", regs.rbx);
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print_reg("rcx", regs.rcx);
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print_reg("rdx", regs.rdx);
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print_reg("rdi", regs.rdi);
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print_reg("rsi", regs.rsi);
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cons->puts("\n");
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print_reg("rbp", regs.rbp);
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print_reg("rsp", regs.rsp);
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cons->puts("\n");
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print_reg("rip", regs.rip);
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print_stacktrace(2);
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}
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while(1) asm("hlt");
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break;
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default:
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cons->set_color(9);
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cons->puts("\nReceived ISR interrupt:\n");
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cons->set_color();
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cons->printf(" ISR: %02lx\n", regs.interrupt);
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cons->printf(" ERR: %lx\n", regs.errorcode);
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cons->puts("\n");
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print_reg(" ds", regs.ds);
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print_reg("rdi", regs.rdi);
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print_reg("rsi", regs.rsi);
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print_reg("rbp", regs.rbp);
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print_reg("rsp", regs.rsp);
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print_reg("rbx", regs.rbx);
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print_reg("rdx", regs.rdx);
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print_reg("rcx", regs.rcx);
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print_reg("rax", regs.rax);
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cons->puts("\n");
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print_reg("rip", regs.rip);
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print_reg(" cs", regs.cs);
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print_reg(" ef", regs.eflags);
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print_reg("esp", regs.user_esp);
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print_reg(" ss", regs.ss);
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cons->puts("\n");
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print_stacktrace(2);
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while(1) asm("hlt");
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}
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*reinterpret_cast<uint32_t *>(0xffffff80fee000b0) = 0;
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}
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void
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irq_handler(registers regs)
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{
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console *cons = console::get();
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uint8_t irq = get_irq(regs.interrupt);
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if (! device_manager::get().dispatch_irq(irq)) {
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cons->set_color(11);
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cons->printf("\nReceived unknown IRQ: %d (vec %d)\n",
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irq, regs.interrupt);
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cons->set_color();
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print_reg(" ds", regs.ds);
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print_reg("rdi", regs.rdi);
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print_reg("rsi", regs.rsi);
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print_reg("rbp", regs.rbp);
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print_reg("rsp", regs.rsp);
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print_reg("rbx", regs.rbx);
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print_reg("rdx", regs.rdx);
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print_reg("rcx", regs.rcx);
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print_reg("rax", regs.rax);
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cons->puts("\n");
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print_reg("rip", regs.rip);
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print_reg(" cs", regs.cs);
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print_reg(" ef", regs.eflags);
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print_reg("esp", regs.user_esp);
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print_reg(" ss", regs.ss);
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while(1) asm("hlt");
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}
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*reinterpret_cast<uint32_t *>(0xffffff80fee000b0) = 0;
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}
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void
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gdt_dump(const table_ptr &table)
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{
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console *cons = console::get();
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cons->printf(" GDT: loc:%lx size:%d\n", table.base, table.limit+1);
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int count = (table.limit + 1) / sizeof(gdt_descriptor);
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const gdt_descriptor *gdt =
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reinterpret_cast<const gdt_descriptor *>(table.base);
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for (int i = 0; i < count; ++i) {
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uint32_t base =
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(gdt[i].base_high << 24) |
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(gdt[i].base_mid << 16) |
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gdt[i].base_low;
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uint32_t limit =
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static_cast<uint32_t>(gdt[i].size & 0x0f) << 16 |
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gdt[i].limit_low;
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cons->printf(" %02d:", i);
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if (! bitfield_has(gdt[i].type, gdt_type::present)) {
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cons->puts(" Not Present\n");
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continue;
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}
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cons->printf(" Base %08x limit %05x ", base, limit);
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switch (gdt[i].type & gdt_type::ring3) {
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case gdt_type::ring3: cons->puts("ring3"); break;
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case gdt_type::ring2: cons->puts("ring2"); break;
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case gdt_type::ring1: cons->puts("ring1"); break;
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default: cons->puts("ring0"); break;
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}
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cons->printf(" %s %s %s %s %s %s %s\n",
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bitfield_has(gdt[i].type, gdt_type::accessed) ? "A" : " ",
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bitfield_has(gdt[i].type, gdt_type::read_write) ? "RW" : " ",
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bitfield_has(gdt[i].type, gdt_type::conforming) ? "C" : " ",
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bitfield_has(gdt[i].type, gdt_type::execute) ? "EX" : " ",
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bitfield_has(gdt[i].type, gdt_type::system) ? "S" : " ",
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(gdt[i].size & 0x80) ? "KB" : " B",
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(gdt[i].size & 0x60) == 0x20 ? "64" :
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(gdt[i].size & 0x60) == 0x40 ? "32" : "16");
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}
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}
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void
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idt_dump(const table_ptr &table)
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{
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log::info(logs::boot, "Loaded IDT at: %lx size: %d bytes", table.base, table.limit+1);
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int count = (table.limit + 1) / sizeof(idt_descriptor);
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const idt_descriptor *idt =
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reinterpret_cast<const idt_descriptor *>(table.base);
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for (int i = 0; i < count; ++i) {
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uint64_t base =
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(static_cast<uint64_t>(idt[i].base_high) << 32) |
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(static_cast<uint64_t>(idt[i].base_mid) << 16) |
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idt[i].base_low;
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char const *type;
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switch (idt[i].flags & 0xf) {
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case 0x5: type = " 32tsk "; break;
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case 0x6: type = " 16int "; break;
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case 0x7: type = " 16trp "; break;
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case 0xe: type = " 32int "; break;
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case 0xf: type = " 32trp "; break;
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default: type = " ????? "; break;
|
|
}
|
|
|
|
if (idt[i].flags & 0x80) {
|
|
log::debug(logs::boot,
|
|
" Entry %3d: Base:%lx Sel(rpl %d, ti %d, %3d) IST:%d %s DPL:%d", i, base,
|
|
(idt[i].selector & 0x3),
|
|
((idt[i].selector & 0x4) >> 2),
|
|
(idt[i].selector >> 3),
|
|
idt[i].ist,
|
|
type,
|
|
((idt[i].flags >> 5) & 0x3));
|
|
}
|
|
}
|
|
}
|