Pass CPU state as a pointer
Previously CPU statue was passed on the stack, but the compiler is allowed to clobber values passed to it on the stack in the SysV x86 ABI. So now leave the state on the stack but pass a pointer to it into the ISR functions.
This commit is contained in:
@@ -18,8 +18,8 @@ static const uint16_t PIC2 = 0xa0;
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extern "C" {
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void _halt();
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uintptr_t isr_handler(uintptr_t, cpu_state);
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uintptr_t irq_handler(uintptr_t, cpu_state);
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uintptr_t isr_handler(uintptr_t, cpu_state*);
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uintptr_t irq_handler(uintptr_t, cpu_state*);
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uintptr_t syscall_handler(uintptr_t, cpu_state);
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#define ISR(i, name) extern void name ();
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@@ -105,23 +105,23 @@ interrupts_init()
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}
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uintptr_t
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isr_handler(uintptr_t return_rsp, cpu_state regs)
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isr_handler(uintptr_t return_rsp, cpu_state *regs)
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{
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console *cons = console::get();
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switch (static_cast<isr>(regs.interrupt & 0xff)) {
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switch (static_cast<isr>(regs->interrupt & 0xff)) {
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case isr::isrGPFault: {
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cons->set_color(9);
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cons->puts("\nGeneral Protection Fault:\n");
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cons->set_color();
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cons->printf(" errorcode: %lx", regs.errorcode);
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if (regs.errorcode & 0x01) cons->puts(" external");
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cons->printf(" errorcode: %lx", regs->errorcode);
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if (regs->errorcode & 0x01) cons->puts(" external");
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int index = (regs.errorcode & 0xffff) >> 4;
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int index = (regs->errorcode & 0xffff) >> 4;
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if (index) {
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switch ((regs.errorcode & 0x07) >> 1) {
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switch ((regs->errorcode & 0x07) >> 1) {
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case 0:
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cons->printf(" GDT[%x]\n", index);
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gdt_dump();
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@@ -140,10 +140,10 @@ isr_handler(uintptr_t return_rsp, cpu_state regs)
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} else {
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cons->putc('\n');
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}
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print_regs(regs);
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print_regs(*regs);
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/*
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print_stacktrace(2);
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print_stack(regs);
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print_stack(*regs);
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*/
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}
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@@ -156,19 +156,19 @@ isr_handler(uintptr_t return_rsp, cpu_state regs)
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cons->set_color();
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cons->puts(" flags:");
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if (regs.errorcode & 0x01) cons->puts(" present");
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if (regs.errorcode & 0x02) cons->puts(" write");
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if (regs.errorcode & 0x04) cons->puts(" user");
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if (regs.errorcode & 0x08) cons->puts(" reserved");
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if (regs.errorcode & 0x10) cons->puts(" ip");
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if (regs->errorcode & 0x01) cons->puts(" present");
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if (regs->errorcode & 0x02) cons->puts(" write");
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if (regs->errorcode & 0x04) cons->puts(" user");
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if (regs->errorcode & 0x08) cons->puts(" reserved");
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if (regs->errorcode & 0x10) cons->puts(" ip");
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cons->puts("\n");
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uint64_t cr2 = 0;
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__asm__ __volatile__ ("mov %%cr2, %0" : "=r"(cr2));
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print_reg("cr2", cr2);
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print_reg("rsp", regs.user_rsp);
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print_reg("rip", regs.rip);
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print_reg("rsp", regs->user_rsp);
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print_reg("rip", regs->rip);
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cons->puts("\n");
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print_stacktrace(2);
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@@ -192,14 +192,14 @@ isr_handler(uintptr_t return_rsp, cpu_state regs)
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case isr::isrAssert: {
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cons->set_color();
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print_regs(regs);
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print_regs(*regs);
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print_stacktrace(2);
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}
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_halt();
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break;
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case isr::isrSyscall: {
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return_rsp = syscall_dispatch(return_rsp, regs);
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return_rsp = syscall_dispatch(return_rsp, *regs);
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}
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break;
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@@ -215,7 +215,7 @@ isr_handler(uintptr_t return_rsp, cpu_state regs)
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case isr::isrIgnore5:
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case isr::isrIgnore6:
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case isr::isrIgnore7:
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//cons->printf("\nIGNORED: %02x\n", regs.interrupt);
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//cons->printf("\nIGNORED: %02x\n", regs->interrupt);
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outb(PIC1, 0x20);
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break;
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@@ -227,7 +227,7 @@ isr_handler(uintptr_t return_rsp, cpu_state regs)
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case isr::isrIgnoreD:
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case isr::isrIgnoreE:
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case isr::isrIgnoreF:
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//cons->printf("\nIGNORED: %02x\n", regs.interrupt);
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//cons->printf("\nIGNORED: %02x\n", regs->interrupt);
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outb(PIC1, 0x20);
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outb(PIC2, 0x20);
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break;
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@@ -235,13 +235,13 @@ isr_handler(uintptr_t return_rsp, cpu_state regs)
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default:
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cons->set_color(9);
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cons->printf("\nReceived %02x interrupt:\n",
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(static_cast<isr>(regs.interrupt)));
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(static_cast<isr>(regs->interrupt)));
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cons->set_color();
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cons->printf(" ISR: %02lx ERR: %lx\n\n",
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regs.interrupt, regs.errorcode);
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regs->interrupt, regs->errorcode);
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print_regs(regs);
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print_regs(*regs);
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//print_stacktrace(2);
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_halt();
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}
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@@ -251,16 +251,16 @@ isr_handler(uintptr_t return_rsp, cpu_state regs)
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}
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uintptr_t
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irq_handler(uintptr_t return_rsp, cpu_state regs)
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irq_handler(uintptr_t return_rsp, cpu_state *regs)
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{
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console *cons = console::get();
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uint8_t irq = get_irq(regs.interrupt);
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uint8_t irq = get_irq(regs->interrupt);
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if (! device_manager::get().dispatch_irq(irq)) {
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cons->set_color(11);
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cons->printf("\nReceived unknown IRQ: %d (vec %d)\n",
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irq, regs.interrupt);
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irq, regs->interrupt);
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cons->set_color();
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print_regs(regs);
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print_regs(*regs);
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_halt();
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}
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@@ -6,6 +6,7 @@ isr_handler_prelude:
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push_all_and_segments
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mov rdi, rsp
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mov rsi, rsp
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call isr_handler
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mov rsp, rax
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@@ -21,6 +22,7 @@ irq_handler_prelude:
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push_all_and_segments
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mov rdi, rsp
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mov rsi, rsp
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call irq_handler
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mov rsp, rax
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@@ -56,8 +58,8 @@ irq_handler_prelude:
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jmp irq_handler_prelude
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%endmacro
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%define EISR(i, name) EMIT_EISR name, i
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%define UISR(i, name) EMIT_ISR name, i
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%define EISR(i, name) EMIT_EISR name, i ; ISR with error code
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%define UISR(i, name) EMIT_ISR name, i ; ISR callable from user space
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%define ISR(i, name) EMIT_ISR name, i
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%define IRQ(i, q, name) EMIT_IRQ name, i
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@@ -10,7 +10,7 @@ class lapic;
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struct page_table;
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struct cpu_state;
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extern "C" uintptr_t isr_handler(uintptr_t, cpu_state);
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extern "C" uintptr_t isr_handler(uintptr_t, cpu_state*);
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/// The task scheduler
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@@ -59,8 +59,8 @@ public:
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static scheduler & get() { return s_instance; }
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private:
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friend uintptr_t syscall_dispatch(uintptr_t, const cpu_state &);
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friend uintptr_t isr_handler(uintptr_t, cpu_state);
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friend uintptr_t syscall_dispatch(uintptr_t, cpu_state &);
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friend uintptr_t isr_handler(uintptr_t, cpu_state*);
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/// Handle a timer tick
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/// \arg rsp0 The stack pointer of the current interrupt handler
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@@ -35,7 +35,7 @@ syscall_enable()
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}
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uintptr_t
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syscall_dispatch(uintptr_t return_rsp, const cpu_state ®s)
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syscall_dispatch(uintptr_t return_rsp, cpu_state ®s)
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{
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console *cons = console::get();
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syscall call = static_cast<syscall>(regs.rax);
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@@ -65,7 +65,7 @@ syscall_dispatch(uintptr_t return_rsp, const cpu_state ®s)
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auto *p = s.current();
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p->wait_on_signal(-1ull);
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cons->printf("\nReceived PAUSE syscall\n");
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return_rsp = s.tick(return_rsp);
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return_rsp = s.schedule(return_rsp);
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cons->set_color();
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}
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break;
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@@ -78,7 +78,7 @@ syscall_dispatch(uintptr_t return_rsp, const cpu_state ®s)
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auto *p = s.current();
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p->wait_on_time(regs.rbx);
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cons->printf("\nReceived SLEEP syscall\n");
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return_rsp = s.tick(return_rsp);
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return_rsp = s.schedule(return_rsp);
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cons->set_color();
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}
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break;
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@@ -16,5 +16,5 @@ enum class syscall : uint64_t
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};
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void syscall_enable();
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uintptr_t syscall_dispatch(uintptr_t, const cpu_state &);
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uintptr_t syscall_dispatch(uintptr_t, cpu_state &);
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