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90663a674a
Previously, the CPU control registers were being set in a number of different ways. Now, since the APs' need this to be set in the CPU initialization code, always do it there. This removes some of the settings from the bootloader, and some unused ones from smp.s. Additionally, the control registers' flags are now enums in cpu.h and manipulated via util::bitset.
133 lines
3.0 KiB
C++
133 lines
3.0 KiB
C++
#pragma once
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#include <stdint.h>
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class GDT;
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class IDT;
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class lapic;
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struct TCB;
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class TSS;
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namespace obj {
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class process;
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class thread;
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}
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enum class cr0
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{
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PE = 0, // Protected mode enable
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MP = 1, // Monitor co-processor
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ET = 4, // Extension type
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NE = 5, // Numeric error
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WP = 16, // (ring 0) Write protect
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PG = 31, // Paging
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};
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enum class cr4
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{
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DE = 3, // Debugging extensions
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PAE = 5, // Physical address extension
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MCE = 6, // Machine check exception
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PGE = 7, // Page global enable
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OSXFSR = 9, // OS supports FXSAVE
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OSXMMEXCPT = 10, // OS supports SIMD FP exceptions
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FSGSBASE = 16, // Enable {RD|WR}{F|G}SBASE instructions
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PCIDE = 17, // PCID enable
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OSXSAVE = 18, // OS supports XSAVE and extended states
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};
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enum class xcr0
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{
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X87,
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SSE,
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AVX,
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BINDREG,
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BINDCSR,
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OPMASK,
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ZMM_Hi256,
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ZMM_Hi16,
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PKRU = 9,
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};
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enum class efer
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{
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SCE = 0, // System call extensions (SYSCALL/SYSRET)
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LME = 8, // Long mode enable
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LMA = 10, // Long mode active
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NXE = 11, // No-execute enable
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FFXSR = 14, // Fast FXSAVE
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};
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struct cpu_state
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{
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uint64_t r15, r14, r13, r12, r11, r10, r9, r8;
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uint64_t rdi, rsi, rbp, rbx, rdx, rcx, rax;
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uint64_t interrupt, errorcode;
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uint64_t rip, cs, rflags, rsp, ss;
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};
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/// Kernel-wide panic information
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struct panic_data
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{
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void const *symbol_data;
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cpu_state const *user_state;
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char const *message;
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char const *function;
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char const *file;
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uint32_t line;
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uint16_t cpus;
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};
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extern unsigned g_num_cpus;
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extern panic_data *g_panic_data_p;
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/// Per-cpu state data. If you change this, remember to update the assembly
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/// version in 'tasking.inc'
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struct cpu_data
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{
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cpu_data *self;
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uint16_t id;
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uint16_t index;
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uint32_t reserved;
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uintptr_t rsp0;
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uintptr_t rsp3;
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uint64_t rflags3;
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TCB *tcb;
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obj::thread *thread;
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obj::process *process;
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IDT *idt;
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TSS *tss;
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GDT *gdt;
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// Members beyond this point do not appear in
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// the assembly version
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lapic *apic;
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panic_data *panic;
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};
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extern "C" cpu_data * _current_gsbase();
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/// Do early initialization of the BSP CPU.
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/// \returns A pointer to the BSP cpu_data structure
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cpu_data * bsp_early_init();
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/// Do late initialization of the BSP CPU.
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void bsp_late_init();
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/// Create a new cpu_data struct with all requisite sub-objects.
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/// \arg id The ACPI specified id of the CPU
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/// \arg index The kernel-specified initialization index of the CPU
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/// \returns The new cpu_data structure
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cpu_data * cpu_create(uint16_t id, uint16_t index);
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/// Set up the running CPU. This sets GDT, IDT, and necessary MSRs as well as creating
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/// the cpu_data structure for this processor.
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/// \arg cpu The cpu_data structure for this CPU
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/// \arg bsp True if this CPU is the BSP
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void cpu_init(cpu_data *cpu, bool bsp);
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/// Get the cpu_data struct for the current executing CPU
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inline cpu_data & current_cpu() { return *_current_gsbase(); }
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