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2d4a65c654
In order to avoid cyclic dependencies in the case of page faults while bringing up an AP, pre-allocate the cpu_data structure and related CPU control structures, and pass them to the AP startup code. This also changes the following: - cpu_early_init() was split out of cpu_early_init() to allow early usage of current_cpu() on the BSP before we're ready for the rest of cpu_init(). (These functions were also renamed to follow the preferred area_action naming style.) - isr_handler now zeroes out the IST entry for its vector instead of trying to increment the IST stack pointer - the IST stacks are allocated outside of cpu_init, to also help reduce stack pressue and chance of page faults before APs are ready - share stack areas between AP idle threads so we only waste 1K per additional AP for the unused idle stack
138 lines
3.1 KiB
C++
138 lines
3.1 KiB
C++
#include "kutil/memory.h"
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#include "kutil/no_construct.h"
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#include "idt.h"
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#include "log.h"
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extern "C" {
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void idt_write(const void *idt_ptr);
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#define ISR(i, s, name) extern void name ();
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#define EISR(i, s, name) extern void name ();
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#define IRQ(i, q, name) extern void name ();
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#include "interrupt_isrs.inc"
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#undef IRQ
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#undef EISR
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#undef ISR
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}
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// The IDT is initialized _before_ global constructors are called,
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// so we don't want it to have a global constructor, lest it overwrite
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// the previous initialization.
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static kutil::no_construct<IDT> __g_idt_storage;
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IDT &g_idt = __g_idt_storage.value;
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IDT::IDT()
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{
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kutil::memset(this, 0, sizeof(IDT));
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m_ptr.limit = sizeof(m_entries) - 1;
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m_ptr.base = &m_entries[0];
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#define ISR(i, s, name) set(i, & name, 0x08, 0x8e);
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#define EISR(i, s, name) set(i, & name, 0x08, 0x8e);
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#define IRQ(i, q, name) set(i, & name, 0x08, 0x8e);
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#include "interrupt_isrs.inc"
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#undef IRQ
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#undef EISR
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#undef ISR
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}
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IDT &
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IDT::get()
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{
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return g_idt;
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}
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void
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IDT::install() const
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{
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idt_write(static_cast<const void*>(&m_ptr));
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}
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void
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IDT::add_ist_entries()
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{
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#define ISR(i, s, name) if (s) { set_ist(i, s); }
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#define EISR(i, s, name) if (s) { set_ist(i, s); }
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#define IRQ(i, q, name)
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#include "interrupt_isrs.inc"
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#undef IRQ
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#undef EISR
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#undef ISR
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}
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uint8_t
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IDT::used_ist_entries() const
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{
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uint8_t entries = 0;
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#define ISR(i, s, name) if (s) { entries |= (1 << s); }
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#define EISR(i, s, name) if (s) { entries |= (1 << s); }
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#define IRQ(i, q, name)
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#include "interrupt_isrs.inc"
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#undef IRQ
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#undef EISR
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#undef ISR
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return entries;
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}
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void
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IDT::set(uint8_t i, void (*handler)(), uint16_t selector, uint8_t flags)
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{
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uintptr_t addr = reinterpret_cast<uintptr_t>(handler);
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m_entries[i].base_low = addr & 0xffff;
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m_entries[i].base_mid = (addr >> 16) & 0xffff;
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m_entries[i].base_high = (addr >> 32) & 0xffffffff;
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m_entries[i].selector = selector;
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m_entries[i].flags = flags;
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m_entries[i].ist = 0;
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m_entries[i].reserved = 0;
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}
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void
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IDT::dump(unsigned index) const
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{
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unsigned start = 0;
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unsigned count = (m_ptr.limit + 1) / sizeof(descriptor);
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if (index != -1) {
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start = index;
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count = 1;
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log::info(logs::boot, "IDT FOR INDEX %02x", index);
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} else {
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log::info(logs::boot, "Loaded IDT at: %lx size: %d bytes", m_ptr.base, m_ptr.limit+1);
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}
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const descriptor *idt =
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reinterpret_cast<const descriptor *>(m_ptr.base);
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for (int i = start; i < start+count; ++i) {
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uint64_t base =
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(static_cast<uint64_t>(idt[i].base_high) << 32) |
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(static_cast<uint64_t>(idt[i].base_mid) << 16) |
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idt[i].base_low;
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char const *type;
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switch (idt[i].flags & 0xf) {
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case 0x5: type = " 32tsk "; break;
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case 0x6: type = " 16int "; break;
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case 0x7: type = " 16trp "; break;
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case 0xe: type = " 32int "; break;
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case 0xf: type = " 32trp "; break;
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default: type = " ????? "; break;
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}
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if (idt[i].flags & 0x80) {
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log::debug(logs::boot,
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" Entry %3d: Base:%lx Sel(rpl %d, ti %d, %3d) IST:%d %s DPL:%d", i, base,
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(idt[i].selector & 0x3),
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((idt[i].selector & 0x4) >> 2),
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(idt[i].selector >> 3),
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idt[i].ist,
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type,
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((idt[i].flags >> 5) & 0x3));
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}
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}
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}
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